Everspin Technologies

15 years ago, Everspin MRAM was already at work in data centers. One of the early uses was journal memory in RAID systems, retaining information used to rebuild the RAID faster after a crash. From there, MRAM moved into persistent write buffering and caching. Today, Everspin has demonstrated CXL-connected MRAM, with potential applications including AI checkpointing and persistent KV cache. That history adds some context to a new EE Times | Electronic Engineering Times interview where Yashasvini Razdan talks with our President and CEO Sanjeev Aggarwal about what Everspin is working on now, from CXL-connected MRAM and higher-density STT-MRAM to MRAM in satellite systems. Read the full interview in EE Times: https://lnkd.in/gkSkbH4G #MRAM #STTMRAM #DataCenters #AI #Semiconductors

LPDDR and persistent memory are now part of the same standards conversation. JEDEC has formed a new task group exploring how persistent memory could work within the LPDDR ecosystem, and Everspin’s Steffen Hellmold is chairing the effort. Standards get shaped by the companies at the table, and this group already includes participants from across the ecosystem, including companies in the semiconductor, memory, storage, controller and hyperscale data center markets. The work is already underway, and we’re excited to be a part of what comes next. More on the task group and Everspin’s role: https://lnkd.in/gMUUY_E8 #MRAM #PersistentMemory #LPDDR #Semiconductors

Beyond the excitement of ringing the Opening Bell Thursday, it was an opportunity to reconnect, build relationships and celebrate how far we’ve come together. Thank you to everyone who joined us and helped make the occasion so special. Here’s a look at some of our favorite moments! #Everspin #Nasdaq #MRAM

Everspin's MRAM history didn't begin with the IPO, it stretches from early MRAM research at Motorola, through Freescale and the first commercial MRAM product, to the formation of Everspin, Nasdaq and the applications being served today. Here is the short version of how Everspin got here. This is the first in a Friday series where we’ll be looking back at the milestones that shaped Everspin and the technology along the way. 10 Years on Nasdaq. 18+ Years in Production. #MRAM #HistoryofEverspin #Semiconductors

At SNIA Developer Conference (SDC) 2026, we demonstrated the world’s first CXL-connected MRAM platform. The working system adds a fast persistent memory tier between DRAM and NAND, with memory-semantic access, cache-line-level, nanosecond-class access and writes up to 100x faster than NAND-based solid-state storage. Data remains available through a power interruption or system restart without relying on battery-backed DRAM or first flushing to an SSD. The demo runs on a Supermicro AS-1116CS-TN server with an AMD EPYC 9355 processor, an AMD Alveo U250 FPGA platform with a Wolley Inc. CXL controller and Everspin PERSYST 1GB DDR4 MRAM UDIMMs. For AI systems, that creates opportunities for applications such as checkpointing and persistent key-value cache. As Sanjeev Aggarwal, our president and CEO, said: “We now have a working system so customers can run their own workloads and measure the benefit for their specific applications.” Read the full announcement: https://lnkd.in/gHZyiMWz #MRAM #CXL #DataCenters #PersistentMemory #AIInfrastructure

Space missions are not all the same, and neither are their memory requirements. In his latest SpaceNews op-ed, Sean Dougherty looks at how aerospace and satellite designers can think differently about memory selection and where MRAM can fit. Which leads to the question: “Do you really need space-grade components?” Read Sean’s SpaceNews op-ed: https://lnkd.in/g4na9hqV #MRAM #Space #Aerospace #Semiconductors #SatelliteTechnology