AMIQ EDA

Hardware Design and Verification Engineers at your company are probably using AMIQ EDA tools to boost their productivity. Are you?

Our productivity tools may already be available within your company. Check your engineering toolbox and take full advantage of it.

We're getting ready to say hi to our friends in #Munich. Our newsletter subscribers got the early update, now we're sharing the news with everyone: we'll be at DVCon Europe 2025! Meet our team at Booth #07, on October 14-15. We’ll walk you through the product updates that defined 2025 and share what we’re preparing for the months ahead. #dvconeu #semiconductors #techconference

Couldn’t make it to DVCon Europe 2025? Take a quick look at what’s new in DVT IDE lately: 🧠 AI Assistant can use DVT tools for accurate insights about your design and testbench. 📝 With the help of AI Assistant, you can generate, preview, and fine-tune documentation right in the IDE. 📈 You can visualize signals from simulation trace files, jump instantly between code and waveform, and add signals straight from the editor. More details in the press release: https://lnkd.in/dHft-Q7A #DVT #EDA #DVConEurope #Verification #DesignAutomation

A weight of 0.5 sounds like half the chance, right? Not necessarily. In this edition of our SystemVerilog Pitfalls series, we look at why fractional randomization weights can lead to unexpected results, explore a solution that seems plausible but isn’t, and share the approach that does. P.S. #Verissimo #SystemVerilog Linter can flag fractional weights to help you avoid this pitfall in the first place. #AMIQEDA #verification

Small details like these can make the difference in #SystemVerilog: when local variables are initialized and when processes spawned by fork-join actually start executing. Our latest SystemVerilog Pitfalls article explores this race condition, including two working approaches and one seemingly correct solution that doesn’t actually solve it.