Marvell Technology

At Investor Day, Xi Wang, SVP and GM of Connectivity, showed how Marvell has been first at every generation, from 200G to 1.6T and now 3.2T, with the DSP, TIA and driver built together as one platform. Marvell is shipping 1.6T today and demonstrated industry-first 2nm solutions for 3.2T live at ECOC, including 400G-per-lane PAM4 and coherent-lite That 25+ years of high-speed analog leadership is how Marvell continues to lead the speed and bandwidth for every transition. Watch the full presentation: https://mrvl.co/3TzCLBM

The next frontier for AI connectivity is connecting AI clusters across data centers up to 1,000 km apart. At Investor Day, Russ Esmacher, SVP and GM, Data Center Interconnect, explained why scale-across is a step change for DCI: ~15x the bandwidth of traditional DCI, and a pull toward 1.6T and 3.2T coherent pluggables. Marvell led the shift to coherent pluggables a decade ago and has shipped more than a million. Now it's bringing 2nm-powered 1.6T modules to market and investing in 3.2T. Watch the full presentation: https://mrvl.co/3TzCLBM

The XPU is only part of the story. At Investor Day, Will Chu, EVP and GM of the Custom Cloud Solutions Business, showed how hyperscalers are pulling Marvell in to optimize the infrastructure around the XPU. Alongside custom NICs, memory expansion and storage, two new categories are emerging: AI infrastructure management silicon, and inference accelerators that offload work from the XPU. These XPU attach programs build on proven Marvell IP and are multi-generational by design. Watch the full presentation: https://mrvl.co/3TzCLBM

Behind every growth number is an operating engine built to deliver it. At Investor Day, President and COO Chris Koopmans showed how Marvell scales for AI: deep hyperscaler partnerships, a talent pipeline and AI-native design flow, and supply chain relationships built on trust. Marvell is building for the long-term, at scale. Watch the full presentation: https://mrvl.co/3TzCLBM

The Next Platform took a deep dive into the Marvell Teralynx T100, including a rare die shot of the switch ASIC itself. Timothy Prickett Morgan breaks down what makes the T100 distinctive: a monolithic 3nm design pushing reticle limits, 512 working SerDes delivering 102.4 Tbps of aggregate bandwidth, port-to-port latency of 420 nanoseconds, and power consumption under 1,000 watts. The piece also covers the full range of packaging options, from BGA to co-packaged copper to CPO, and the roadmap ahead including ESUN and UALink switch variants. For a technically detailed look at one of the most consequential switch ASICs in recent memory, this is worth the read: https://mrvl.co/4vFk908

Scaling AI isn’t just a performance challenge. It’s a power and density problem. Inside the rack, connections outnumber those between racks by 10×, pushing traditional optical approaches beyond their limits. That’s why the industry is moving to co-packaged optics (CPO). At COMPUTEX 2026, Marvell Chairman and Chief Executive Officer Matt Murphy showcased a Marvell 100Tbps Teralynx switch and a next-generation CPO-based switch. Purpose-built to deliver the bandwidth, efficiency, and density required for AI at scale. See the video: https://mrvl.co/4vZLsDq